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ISCA
2012
IEEE
274views Hardware» more  ISCA 2012»
13 years 9 months ago
The dynamic granularity memory system
Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Ma...
VLSID
2004
IEEE
85views VLSI» more  VLSID 2004»
16 years 6 months ago
An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
ISCAS
2007
IEEE
144views Hardware» more  ISCAS 2007»
16 years 24 days ago
Quasi-Resonant Interconnects: A Low Power Design Methodology
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
Jonathan Rosenfeld, Eby G. Friedman
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
16 years 3 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
VTC
2008
IEEE
186views Communications» more  VTC 2008»
16 years 27 days ago
Combination of Dynamic-TDD and Static-TDD Based on Adaptive Power Control
— To support dynamic traffic-asymmetry property in future wireless communication systems, we propose a hybridTDD scheme, combination of static-TDD and dynamic-TDD. By using adap...
Howon Lee, Dong-Ho Cho