Chip multiprocessors enable continued performance scaling with increasingly many cores per chip. As the throughput of computation outpaces available memory bandwidth, however, the...
Doe Hyun Yoon, Min Kyu Jeong, Michael Sullivan, Ma...
A key component of the Data-Intensive Architecture (DIVA) is the Processing-In-Memory (PIM) Routing Component (PiRC) that is responsible for efficient communication between PIM ch...
Sumit D. Mediratta, Jeff Sondeen, Jeffrey T. Drape...
— Design and analysis guidelines for resonant interconnect networks are presented in this paper. The methodology focuses on developing an accurate analytic distributed model of t...
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
— To support dynamic traffic-asymmetry property in future wireless communication systems, we propose a hybridTDD scheme, combination of static-TDD and dynamic-TDD. By using adap...