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PDP
2010
IEEE
15 years 10 months ago
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications
The increasing numbers of cores, shared caches and memory nodes within machines introduces a complex hardware topology. High-performance computing applications now have to carefull...
François Broquedis, Jérôme Cle...
IPPS
2009
IEEE
16 years 1 months ago
Optimizing assignment of threads to SPEs on the cell BE processor
The Cell is a heterogeneous multicore processor that has attracted much attention in the HPC community. The bulk of the computational workload on the Cell processor is carried by ...
C. Devi Sudheer, T. Nagaraju, Pallav K. Baruah, As...
CCS
2010
ACM
15 years 6 months ago
Recruiting new tor relays with BRAIDS
Tor, a distributed Internet anonymizing system, relies on volunteers who run dedicated relays. Other than altruism, these volunteers have no incentive to run relays, causing a lar...
Rob Jansen, Nicholas Hopper, Yongdae Kim
IPPS
1998
IEEE
15 years 10 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...
ICPP
2008
IEEE
16 years 26 days ago
Memory Access Scheduling Schemes for Systems with Multi-Core Processors
On systems with multi-core processors, the memory access scheduling scheme plays an important role not only in utilizing the limited memory bandwidth but also in balancing the pro...
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zh...