1765 search results - page 118 / 353 » Communication Scheduling |
160
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IPPS
1998
IEEE
15 years 10 months ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
131
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DATE
2007
IEEE
16 years 14 days ago
2007
IEEE
In this paper we propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified b...
164
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IPPS
2006
IEEE
16 years 5 days ago
2006
IEEE
With the increasing importance of energy consumption considerations and new requirements of emerging applications, in-network processing of information gains recognition as a viab...
170
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PROCEDIA
2010
15 years 27 days ago
2010
High performance computing with low cost machines becomes a reality with GPU. Unfortunately, high performances are achieved when the programmer exploits the architectural specific...
168
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ICPP
1997
IEEE
15 years 10 months ago
1997
IEEE
r The lack of a versatile software tool for parallel program development has been one of the major obstacles for exploiting the potential of high-performance architectures. In this...