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DATE
2007
IEEE
97views Hardware» more  DATE 2007»
16 years 1 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
DFT
2007
IEEE
86views VLSI» more  DFT 2007»
16 years 1 months ago
Production Yield and Self-Configuration in the Future Massively Defective Nanochips
We address two problems in this work, namely, 1) the resilience challenge in the future chips made up of massively defective nanoelements and organized in replicative multicore ar...
Piotr Zajac, Jacques Henri Collet
DSN
2007
IEEE
16 years 1 months ago
How to Choose a Timing Model?
When employing a consensus algorithm for state machine replication, should one optimize for the case that all communication links are usually timely, or for fewer timely links? Do...
Idit Keidar, Alexander Shraer
GLOBECOM
2007
IEEE
16 years 1 months ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
GLOBECOM
2007
IEEE
16 years 1 months ago
DSR-Based Directional Routing Protocol for Ad Hoc Networks
Abstract— In this paper, a Dynamic Source Routing (DSR)based directional routing protocol is invoked for wireless ad hoc networks using directional antennas. This is designed to ...
Bin Hu, Hamid Gharavi