d Abstract) Alexander Aiken1 and Edward L. Wimmers2 and Jens Palsberg3 1 EECS Department, University of California at Berkeley, Berkeley, CA 94720-1776. 2 IBM Almaden Research Cent...
Shared memory architectures often have caches to reduce the number of slow remote memory accesses. The largest possible caches exist in shared memory architectures called Cache-On...
Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design sp...
In this paper we present an enhanced design flow model that increases the capabilities of a CAD framework to support design activities on hierarchical multi-view design descriptio...
Pieter van der Wolf, K. Olav ten Bosch, Alfred van...
Abstract - Parallel algorithms of the hypercube allocation strategies are considered in this paper. Although the sequential algorithms of various hypercube allocation strategies ar...