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ICCAD
2005
IEEE
98views Hardware» more  ICCAD 2005»
16 years 4 months ago
Clustering for processing rate optimization
Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level m...
Chuan Lin, Jia Wang, Hai Zhou
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
16 years 4 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
DFT
2009
IEEE
154views VLSI» more  DFT 2009»
16 years 2 months ago
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
We propose a framework that allows dual-layer cooperative error control in a nanoscale network-on-chip (NoC), to simultaneously improve reliability, performance and energy efficie...
Qiaoyan Yu, Paul Ampadu
IROS
2009
IEEE
188views Robotics» more  IROS 2009»
16 years 2 months ago
Novelty detection and 3D shape retrieval based on Gaussian Mixture Models for autonomous surveillance robotics
Abstract— This paper describes an efficient method for retrieving the 3-dimensional shape associated to novelties in the environment of an autonomous robot, which is equipped wi...
Pedro Núñez Trujillo, Paulo Drews, R...
DATE
2008
IEEE
78views Hardware» more  DATE 2008»
16 years 1 months ago
Simultaneous FU and Register Binding Based on Network Flow Method
– With the rapid increase of design complexity and the decrease of device features in nano-scale technologies, interconnection optimization in digital systems becomes more and mo...
Jason Cong, Junjuan Xu