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DATE
1999
IEEE
89views Hardware» more  DATE 1999»
15 years 11 months ago
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge...
ICCD
1999
IEEE
86views Hardware» more  ICCD 1999»
15 years 11 months ago
Evaluation of Computing in Memory Architectures for Digital Image Processing Applications
Continuing improvements in semiconductor density are enabling new classes of System-on-a-Chip architectures that combine extensive processing logic and high-density memory. Many o...
David L. Landis, Paul T. Hulina, Scott Deno, Luke ...
IPPS
1998
IEEE
15 years 11 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
ECOOP
1998
Springer
15 years 11 months ago
An Imperative, First-Order Calculus with Object Extension
This paper presents an imperative object calculus designed to support class-based programming via a combination of extensible objects and encapsulation. This calculus simplifies th...
Viviana Bono, Kathleen Fisher
ICC
1997
IEEE
15 years 11 months ago
Performance of Multiuser Detection with Adaptive Channel Estimation
Abstract—An adaptive multipath decorrelating multiuser receiver is considered for application in Rayleigh fading multipath channels with significant Doppler spread. Coherent div...
M. Stojanovic, Z. Zvonar