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EUROPAR
2000
Springer
15 years 10 months ago
Scheduling the Computations of a Loop Nest with Respect to a Given Mapping
Abstract. When parallelizing loop nests for distributed memory parallel computers, we have to specify when the different computations are carried out (computation scheduling), wher...
Alain Darte, Claude G. Diderich, Marc Gengler, Fr&...
PATMOS
2000
Springer
15 years 10 months ago
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
Dimitrios Soudris, Nikolaos D. Zervas, Antonios Ar...
DAC
1995
ACM
15 years 10 months ago
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores
Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade–off between flexibility and cost. However, existing code generation metho...
Adwin H. Timmer, Marino T. J. Strik, Jef L. van Me...
EURODAC
1995
IEEE
137views VHDL» more  EURODAC 1995»
15 years 10 months ago
A formal non-heuristic ATPG approach
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
Manfred Henftling, Hannes C. Wittmann, Kurt Antrei...
ASAP
2008
IEEE
105views Hardware» more  ASAP 2008»
15 years 9 months ago
Fast custom instruction identification by convex subgraph enumeration
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. &Ou...