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ISCAS
1999
IEEE
134views Hardware» more  ISCAS 1999»
15 years 11 months ago
Low power DCT implementation approach for VLSI DSP processors
This paper presents an algorithm for the low power implementation of the Discrete Cosine Transform on Single multiplier CMOS DSPs. The algorithm reduces power by a combination of ...
S. Masupe, T. Arslan
ISCAS
1999
IEEE
92views Hardware» more  ISCAS 1999»
15 years 11 months ago
Hybrid inverse halftoning using adaptive filtering
We propose a novel fast inverse halftoning technique using a combination of spatial varying filtering and spatial invariant filtering. The proposed algorithm is significantly simp...
Oscar C. Au, Ming Sun Fu, Peter H. W. Wong, Justy ...
VTS
1999
IEEE
71views Hardware» more  VTS 1999»
15 years 11 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
DFT
1997
IEEE
101views VLSI» more  DFT 1997»
15 years 11 months ago
Crosstalk Minimization in Three-Layer HVH Channel Routing
Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits...
Zhan Chen, Israel Koren
PPSN
1998
Springer
15 years 11 months ago
Niching and Elitist Models for MOGAs
This paper examines several niching and elitist models applied to Multiple-Objective Genetic Algorithms (MOGAs). Test cases consider a simple problem as well as multidisciplinary d...
Shigeru Obayashi, Shinichi Takahashi, Yukihiro Tak...