838 search results - page 48 / 168 » Combining optimizations in automated low power design |
153
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...
176
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VLSID
2009
IEEE
16 years 6 months ago
2009
IEEE
In this paper, we present a dynamic power management technique for optimizing the use of virtual channels in network on chips. The technique which is called dynamic virtual channe...
193
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CACM
2000
15 years 6 months ago
2000
Wireless Integrated Network Sensors (WINS) now provide a new monitoring and control capability for transportation, manufacturing, health care, environmental monitoring, and safety...
142
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
Estimating switching activity is a crucial step in optimizing circuits for low power. In this paper, a fast gate level switching activity estimator for combinational circuits will...
164
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ASPDAC
1995
ACM
15 years 9 months ago
1995
ACM
A new approach for power analysis of microprocessorshas recently been proposed [1]. The idea is to look at the power consumption in a microprocessor from the point of view of the ...