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ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 16 days ago
A new look at reversible memory elements
Abstract— Although many researchers are investigating techniques to synthesize reversible combinational logic, there is little work in the area of sequential reversible logic. We...
Jacqueline E. Rice
VTS
2006
IEEE
101views Hardware» more  VTS 2006»
16 years 15 days ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
EUROGP
2004
Springer
135views Optimization» more  EUROGP 2004»
15 years 12 months ago
Reusing Code in Genetic Programming
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
Edgar Galván López, Riccardo Poli, C...
FC
2008
Springer
85views Cryptology» more  FC 2008»
15 years 8 months ago
Countermeasures against Government-Scale Monetary Forgery
Abstract. Physical cash is vulnerable to rising threats, such as large-scale, government-mandated forgeries, that digital cash may protect against more effectively. We study mechan...
Alessandro Acquisti, Nicolas Christin, Bryan Parno...
ECAI
2010
Springer
15 years 7 months ago
Parallel Model Checking for Temporal Epistemic Logic
Abstract. We investigate the problem of the verification of multiagent systems by means of parallel algorithms. We present algorithms for CTLK, a logic combining branching time tem...
Marta Z. Kwiatkowska, Alessio Lomuscio, Hongyang Q...