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» Combining Software and Hardware Verification Techniques
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EMSOFT
2008
Springer
15 years 7 months ago
Symbolic analysis for improving simulation coverage of Simulink/Stateflow models
Aimed at verifying safety properties and improving simulation coverage for hybrid systems models of embedded control software, we propose a technique that combines numerical simul...
Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shash...
CODES
2008
IEEE
16 years 13 days ago
You can catch more bugs with transaction level honey
In this special session we explore holistic approaches to hardware/software debug that use or integrate transaction level models (TLMs). We present several TLM-based approaches to...
Miron Abramovici, Kees Goossens, Bart Vermeulen, J...
POPL
2006
ACM
16 years 6 months ago
Certified assembly programming with embedded code pointers
Embedded code pointers (ECPs) are stored handles of functions and continuations commonly seen in low-level binaries as well as functional or higher-order programs. ECPs are known ...
Zhaozhong Ni, Zhong Shao
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
15 years 9 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
DSD
2004
IEEE
129views Hardware» more  DSD 2004»
15 years 9 months ago
Functional Validation of Programmable Architectures
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
Prabhat Mishra, Nikil D. Dutt