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DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
COORDINATION
2008
Springer
15 years 8 months ago
From Flow Logic to Static Type Systems for Coordination Languages
Abstract. Coordination languages are often used to describe open ended systems. This makes it challenging to develop tools for guaranteeing security of the coordinated systems and ...
Rocco De Nicola, Daniele Gorla, René Rydhof...
WWW
2008
ACM
15 years 6 months ago
Flexible Semantic-Based Service Matchmaking and Discovery
Automated techniques and tools are required to effectively locate services that fulfill a given user request in a mobility context. To this purpose, the use of semantic description...
Devis Bianchini, Valeria De Antonellis, Michele Me...
DAC
2007
ACM
16 years 7 months ago
Fast Min-Cost Buffer Insertion under Process Variations
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
Ruiming Chen, Hai Zhou
VMCAI
2010
Springer
16 years 3 months ago
Building a Calculus of Data Structures
Abstract. Techniques such as verification condition generation, preditraction, and expressive type systems reduce software verification to proving formulas in expressive logics. Pr...
Viktor Kuncak, Ruzica Piskac, Philippe Suter, Thom...