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GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
16 years 1 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
TASLP
2008
136views more  TASLP 2008»
15 years 6 months ago
On Acoustic Diversification Front-End for Spoken Language Identification
The parallel phone recognition followed by language model (PPRLM) architecture represents one of the state-of-the-art spoken language identification systems. A PPRLM system compris...
Khe Chai Sim, Haizhou Li
TON
2010
151views more  TON 2010»
15 years 1 months ago
Measurement-Driven Guidelines for 802.11 WLAN Design
Dense deployments of WLANs suffer from increased interference and as a result, reduced capacity. There are three main functions used to improve the overall network capacity: a) in...
Ioannis Broustis, Konstantina Papagiannaki, Srikan...
ICPR
2002
IEEE
16 years 8 months ago
Comparative Study on Mirror Image Learning (MIL) and GLVQ
In this paper the effectiveness of a corrective learning algorithm MIL (Mirror Image Learning) [1], [2] is comparatively studied with that of GLVQ (Generalized Learning Vector Qua...
Meng Shi, Tetsushi Wakabayashi, Wataru Ohyama, Fum...
RTSS
2009
IEEE
16 years 1 months ago
New Response Time Bounds for Fixed Priority Multiprocessor Scheduling
Recently, there have been several promising techniques developed for schedulability analysis and response time analysis for multiprocessor systems based on over-approximation. Thi...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu