Sciweavers

2573 search results - page 379 / 515
» Combinations of Modal Logics
Sort
View
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
15 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 11 months ago
Which concurrent error detection scheme to choose ?
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...
Subhasish Mitra, Edward J. McCluskey
RIDE
1999
IEEE
15 years 10 months ago
Specification of Cooperative Constraints in Virtual Enterprise Workflow
Workflow systems are an emerging technology which have become increasingly important in the drive for business to provide better services and increase productivity. Intuitively, w...
Anne H. H. Ngu
FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
15 years 10 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
DAC
1997
ACM
15 years 10 months ago
Power Macromodeling for High Level Power Estimation
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...
Subodh Gupta, Farid N. Najm