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ICCAD
2006
IEEE
146views Hardware» more  ICCAD 2006»
16 years 3 months ago
An analytical model for negative bias temperature instability
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a significant reliability concern in present day digital circuit design. With continued scaling, th...
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
16 years 1 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia
CCS
2007
ACM
16 years 20 days ago
Specifying and analyzing security automata using CSP-OZ
Security automata are a variant of B¨uchi automata used to specify security policies that can be enforced by monitoring system execution. In this paper, we propose using CSP-OZ, ...
David A. Basin, Ernst-Rüdiger Olderog, Paul E...
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
16 years 15 days ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
MICRO
1998
IEEE
128views Hardware» more  MICRO 1998»
15 years 10 months ago
Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...
Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt