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GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 12 days ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
FPL
2003
Springer
164views Hardware» more  FPL 2003»
15 years 12 months ago
Fast, Large-Scale String Match for a 10Gbps FPGA-Based Network Intrusion Detection System
Intrusion Detection Systems such as Snort scan incoming packets for evidence of security threats. The most computation-intensive part of these systems is a text search against hund...
Ioannis Sourdis, Dionisios N. Pnevmatikatos
INFOCOM
2002
IEEE
15 years 11 months ago
Optimal MAC State Switching for cdma2000 Networks
— This paper deals with the performance modeling of the various MAC states as defined by the cdma2000 protocol. Our method uses a composite performance metric which has the capa...
Mainak Chatterjee, Sajal K. Das
ESORICS
2006
Springer
15 years 10 months ago
Finding Peer-to-Peer File-Sharing Using Coarse Network Behaviors
A user who wants to use a service forbidden by their site's usage policy can masquerade their packets in order to evade detection. One masquerade technique sends prohibited tr...
Michael P. Collins, Michael K. Reiter
FPL
2006
Springer
105views Hardware» more  FPL 2006»
15 years 10 months ago
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an arch...
K. Van Renterghem, Dieter Verhulst, S. Verschuere,...