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SAMOS
2010
Springer
15 years 4 months ago
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
—Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and verification. State-of-the-art simulators using just-in-ti...
Igor Böhm, Björn Franke, Nigel P. Topham
FMAM
2010
157views Formal Methods» more  FMAM 2010»
15 years 4 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
IFM
2010
Springer
183views Formal Methods» more  IFM 2010»
15 years 4 months ago
Certified Absence of Dangling Pointers in a Language with Explicit Deallocation
Safe is a first-order eager functional language with facilities for programmer controlled destruction and copying of data structures. It provides also regions, i.e. disjoint parts...
Javier de Dios, Manuel Montenegro, Ricardo Pe&ntil...
SIPS
2006
IEEE
16 years 16 days ago
Automated Architectural Exploration for Signal Processing Algorithms
Abstract— This paper presents a design environment for efficiently generating application-specific Intellectual Property (IP) cores for system level signal processing algorithm...
Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winse...
PLDI
2006
ACM
16 years 14 days ago
Automatic instruction scheduler retargeting by reverse-engineering
In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a ...
Matthew J. Bridges, Neil Vachharajani, Guilherme O...