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LCTRTS
1999
Springer
15 years 11 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
TACAS
2010
Springer
162views Algorithms» more  TACAS 2010»
16 years 1 months ago
Computing the Leakage of Information-Hiding Systems
We address the problem of computing the information leakage of a system in an efficient way. We propose two methods: one based on reducing the problem to reachability, and the oth...
Miguel E. Andrés, Catuscia Palamidessi, Pet...
CONCUR
2003
Springer
15 years 12 months ago
Priority Rewrite Systems for OSOS Process Languages
We propose an algorithm for generating a Priority Rewrite System (PRS) for an arbitrary process language in the OSOS format such that rewriting of process terms is sound for bisim...
Irek Ulidowski
VLSID
1999
IEEE
139views VLSI» more  VLSID 1999»
15 years 11 months ago
Processor Modeling for Hardware Software Codesign
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
V. Rajesh, Rajat Moona
SC
1995
ACM
15 years 10 months ago
A Novel Approach Towards Automatic Data Distribution
: Data distribution is one of the key aspects that a parallelizing compiler for a distributed memory architecture should consider, in order to get efficiency from the system. The ...
Jordi Garcia, Eduard Ayguadé, Jesús ...