3002 search results - page 403 / 601 » Cloud Based Design Optimization |
161
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ICCAD
2008
IEEE
16 years 29 days ago
2008
IEEE
— The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/O’s in VLSI designs; it can achieve smaller package size, shorter wirelength, an...
176
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SECON
2010
IEEE
15 years 4 months ago
2010
IEEE
Interference model is the basis of MAC protocol design in wireless networks, and it directly affects the efficiency and predictability of wireless messaging. To exploit the strengt...
183
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ICCAD
2009
IEEE
15 years 4 months ago
2009
IEEE
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, ...
168
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DAC
2005
ACM
16 years 7 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
162
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Traditionally, rectilinear Steiner minimum trees (RSMT) are widely used for routing estimation in design optimizations like floorplanning and physical synthesis. Since it optimize...