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ISLPED
2006
ACM
99views Hardware» more  ISLPED 2006»
16 years 17 days ago
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
All existing methods for thermal-via allocation are based on a steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and ...
Hao Yu, Yiyu Shi, Lei He, Tanay Karnik
ISPD
2003
ACM
103views Hardware» more  ISPD 2003»
15 years 12 months ago
An integrated floorplanning with an efficient buffer planning algorithm
Previous works on buffer planning are mainly based on fixed die placement. It is necessary to reduce the complexity of computing the feasible buffer insertion sites to integrate t...
Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, ...
ICCD
2011
IEEE
296views Hardware» more  ICCD 2011»
14 years 6 months ago
DPPC: Dynamic power partitioning and capping in chip multiprocessors
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
Kai Ma, Xiaorui Wang, Yefu Wang
GECCO
2008
Springer
180views Optimization» more  GECCO 2008»
15 years 7 months ago
Bond-graphs + genetic programming: analysis of an automatically synthesized rotary mechanical system
Initial results of an experiment devised to combine Bond-Graph modeling and simulation with genetic programming for automated design of a simple mechatronic system are reported in...
Saheeb Ahmed Kayani, Muhammad Afzaal Malik
ISPASS
2008
IEEE
16 years 1 months ago
Configurational Workload Characterization
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
Hashem Hashemi Najaf-abadi, Eric Rotenberg