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ISCA
1994
IEEE
88views Hardware» more  ISCA 1994»
15 years 11 months ago
A Unified Architectural Tradeoff Methodology
Wepresentaunijiedapp?'each to assess thet7adeoff of architecture techniques that affect mean memory access time. The architectural features we consider inciude cache hit Tati...
Chung-Ho Chen, Arun K. Somani
ASPDAC
2007
ACM
89views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Trace Compaction using SAT-based Reachability Analysis
In today's designs, when functional verification fails, engineers perform debugging using the provided error traces. Reducing the length of error traces can help the debugging...
Sean Safarpour, Andreas G. Veneris, Hratch Mangass...
CMSB
2004
Springer
15 years 10 months ago
Residual Bootstrapping and Median Filtering for Robust Estimation of Gene Networks from Microarray Data
We propose a robust estimation method of gene networks based on microarray gene expression data. It is well-known that microarray data contain a large amount of noise and some outl...
Seiya Imoto, Tomoyuki Higuchi, SunYong Kim, Euna J...
ATVA
2006
Springer
140views Hardware» more  ATVA 2006»
15 years 10 months ago
On the Construction of Fine Automata for Safety Properties
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
Orna Kupferman, Robby Lampert
DAC
2006
ACM
15 years 10 months ago
IMPRES: integrated monitoring for processor reliability and security
Security and reliability in processor based systems are concerns requiring adroit solutions. Security is often compromised by code injection attacks, jeopardizing even `trusted so...
Roshan G. Ragel, Sri Parameswaran