6413 search results - page 227 / 1283 » Classes of cycle bases |
165
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IPPS
2003
IEEE
15 years 12 months ago
2003
IEEE
Exploiting speculative thread-level parallelism across modules, e.g., methods, procedures, or functions, have shown promise. However, misspeculations and task creation overhead ar...
156
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ISCAS
2003
IEEE
15 years 12 months ago
2003
IEEE
The full-custom CMOS realization of a new modular sorting architecture is presented. The high-performance architecture is based on rank ordering, and on efficient implementation o...
172
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ISPD
2003
ACM
15 years 12 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
146
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ISCA
2002
IEEE
15 years 11 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
165
Voted
MICRO
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper we present an approach to boosting performance and tolerating latency by deferring non-critical instructions into a deferred queue for later processing. As such, ins...