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ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
16 years 15 days ago
An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
This paper presents a high-availability system architecture called INDRA — an INtegrated framework for Dependable and Revivable Architecture that enhances a multicore processor ...
Weidong Shi, Hsien-Hsin S. Lee, Laura Falk, Mrinmo...
HPCA
2005
IEEE
16 years 3 days ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
IEEEPACT
2005
IEEE
16 years 2 days ago
Performance Analysis of System Overheads in TCP/IP Workloads
Current high-performance computer systems are unable to saturate the latest available high-bandwidth networks such as 10 Gigabit Ethernet. A key obstacle in achieving 10 gigabits ...
Nathan L. Binkert, Lisa R. Hsu, Ali G. Saidi, Rona...
ISESE
2005
IEEE
16 years 2 days ago
Empirical study design in the area of high-performance computing (HPC)
The development of High-Performance Computing (HPC) programs is crucial to progress in many fields of scientific endeavor. We have run initial studies of the productivity of HPC d...
Forrest Shull, Jeffrey Carver, Lorin Hochstein, Vi...
IWPC
2005
IEEE
16 years 2 days ago
Adding Control-Flow to a Visual Data-Flow Representation
Previous studies have shown that novices do not tend to extract or use data-flow information during program comprehension. However, for impact analysis and similar tasks, data-ï¬...
David Dearman, Anthony Cox, Maryanne Fisher