3395 search results - page 442 / 679 » Circuit-aware architectural simulation |
148
click to vote
INFOCOM
2007
IEEE
16 years 29 days ago
2007
IEEE
—Load-balanced switches have received a great deal of attention recently as they are much more scalable than other existing switch architectures in the literature. However, as th...
139
click to vote
ISCAS
2007
IEEE
16 years 28 days ago
2007
IEEE
—This paper presents a DAC architecture built on parallel current-steering sub-DAC entities. Two main novelties are explored: flexibility and smartness. Firstly, a number of avai...
201
click to vote
ISVLSI
2007
IEEE
16 years 28 days ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
187
Voted
MICRO
2007
IEEE
16 years 28 days ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
177
click to vote
NOCS
2007
IEEE
16 years 28 days ago
2007
IEEE
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...