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DAC
2003
ACM
15 years 12 months ago
Performance trade-off analysis of analog circuits by normal-boundary intersection
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
Guido Stehr, Helmut E. Graeb, Kurt Antreich
DAC
2000
ACM
15 years 11 months ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson
DAC
2000
ACM
15 years 11 months ago
Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability
—Chemical–mechanical polishing (CMP) is an enabling technique used in deep-submicrometer VLSI manufacturing to achieve long range oxide planarization. Post-CMP oxide topography...
Ruiqi Tian, D. F. Wong, Robert Boone
DAC
1998
ACM
16 years 7 months ago
A Programming Environment for the Design of Complex High Speed ASICs
A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiver is used as a driver example. Compact descrip...
Patrick Schaumont, Serge Vernalde, Luc Rijnders, M...
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
16 years 7 months ago
A Heuristic for Peak Power Constrained Design of Network-on-Chip (NoC) Based Multimode Systems
Designing NoC-based systems has become increasingly complex with support for multiple functionalities. Decisions regarding interconnections between the heterogeneous system compon...
Praveen Bhojwani, Rabi N. Mahapatra, Eun Jung Kim,...