3395 search results - page 409 / 679 » Circuit-aware architectural simulation |
110
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ISCAS
2006
IEEE
16 years 21 days ago
2006
IEEE
— Recently, there has been renewed interest in structured logic arrays due to a number of inherent advantages. However, before they will be more widely adopted, structured logic ...
157
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ROBIO
2006
IEEE
16 years 21 days ago
2006
IEEE
— The architecture optimization of a three degrees of freedom (3-DOF) planar cable-driven parallel manipulator (CDPM) with multiple objectives has been implemented by means of GA...
184
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DAC
2006
ACM
16 years 20 days ago
2006
ACM
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
198
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PPOPP
2006
ACM
16 years 19 days ago
2006
ACM
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
154
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WCAE
2006
ACM
16 years 19 days ago
2006
ACM
Learning the various structures and levels of memory hierarchy by means of conventional procedures is a complex subject. A memory hierarchy environment (Web-MHE) was proposed and ...