Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surface...
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
Eric Borch, Eric Tune, Srilatha Manne, Joel S. Eme...