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DAC
2008
ACM
16 years 7 months ago
Predictive design space exploration using genetically programmed response surfaces
Exponential increases in architectural design complexity threaten to make traditional processor design optimization techniques intractable. Genetically programmed response surface...
Henry Cook, Kevin Skadron
VLSID
2006
IEEE
140views VLSI» more  VLSID 2006»
16 years 7 months ago
Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing
A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interco...
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
VLSID
2005
IEEE
89views VLSI» more  VLSID 2005»
16 years 7 months ago
Power Optimization in Current Mode Circuits
We propose a method to minimize power dissipation in current-mode CMOS analog and multiple-valued logic (MVL) circuits employing a stack of current comparators. First, we present ...
M. S. Bhat, H. S. Jamadagni
VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
16 years 7 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson
HPCA
2002
IEEE
16 years 7 months ago
Loose Loops Sink Chips
This paper explores the concept of micro-architectural loops and discusses their impact on processor pipelines. In particular, we establish the relationship between loose loops an...
Eric Borch, Eric Tune, Srilatha Manne, Joel S. Eme...