3395 search results - page 366 / 679 » Circuit-aware architectural simulation |
159
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
183
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SSDBM
1999
IEEE
15 years 11 months ago
1999
IEEE
In many scientific domains, experimental devices or simulation programs generate large volumes of data. The volumes of data may reach hundreds of terabytes and therefore it is imp...
167
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ASYNC
1998
IEEE
15 years 11 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
186
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GLVLSI
1998
IEEE
15 years 11 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
202
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ICPP
1998
IEEE
15 years 11 months ago
1998
IEEE
Exploiting locality at run-time is a complementary approach to a compiler approach for those applications with dynamic memory access patterns. This paper proposes a memory-layout ...