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MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
16 years 23 days ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
CF
2004
ACM
16 years 6 days ago
BLOB computing
Current processor and multiprocessor architectures are almost all based on the Von Neumann paradigm. Based on this paradigm, one can build a general-purpose computer using very fe...
Frédéric Gruau, Yves Lhuillier, Phil...
NOSSDAV
2004
Springer
16 years 3 days ago
Low latency and cheat-proof event ordering for peer-to-peer games
We are developing a distributed architecture for massivelymultiplayer games. In this paper, we focus on designing a low-latency event ordering protocol, called NEO, for this archi...
Chris GauthierDickey, Daniel Zappala, Virginia Mar...
INFOCOM
2003
IEEE
16 years 1 days ago
Network Layer Support for Service Discovery in Mobile Ad Hoc Networks
— Service discovery is an integral part of the ad hoc networking to achieve stand-alone and self-configurable communication networks. In this paper, we discuss possible service ...
Ulas C. Kozat, Leandros Tassiulas
INFOCOM
2003
IEEE
16 years 1 days ago
Exploiting Parallelism to Boost Data-Path Rate in High-Speed IP/MPLS Networking
Abstract—Link bundling is a way to increase routing scalability whenever a pair of Label Switching Routers in MPLS are connected by multiple parallel links. However, link bundlin...
Indra Widjaja, Anwar Elwalid