Sciweavers

3395 search results - page 360 / 679
» Circuit-aware architectural simulation
Sort
View
DAC
2003
ACM
16 years 1 days ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
QOSIP
2001
Springer
15 years 11 months ago
Quality of Service Issues in Multi-service Wireless Internet Links
—Internet application performance over wireless links is disappointing, due to wireless impairments and their adverse interactions with higher protocol layers. In order to effect...
George Xylomenos, George C. Polyzos
IEEEPACT
2000
IEEE
15 years 11 months ago
Exploring the Limits of Sub-Word Level Parallelism
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
Kevin Scott, Jack W. Davidson
VLSID
2008
IEEE
149views VLSI» more  VLSID 2008»
16 years 7 months ago
NBTI Degradation: A Problem or a Scare?
Negative Bias Temperature Instability (NBTI) has been identified as a major and critical reliability issue for PMOS devices in nano-scale designs. It manifests as a negative thres...
Kewal K. Saluja, Shriram Vijayakumar, Warin Sootka...
DSRT
2008
IEEE
16 years 1 months ago
Observability Checking to Enhance Diagnosis of Real Time Electronic Systems
This paper describes a new property checking approach in order to enhance the diagnosis ability of an electronic embedded system, included in an automotive application. We conside...
Manel Khlif, Mohamed Shawky