3395 search results - page 357 / 679 » Circuit-aware architectural simulation |
206
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SIGMETRICS
2011
ACM
14 years 9 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
144
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DAC
2007
ACM
16 years 7 months ago
2007
ACM
This paper describes a family of novel dynamically reconfigurable logic gates based on double-gate carbon nanotube field-effect transistors which demonstrate p-type or n-type switc...
169
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VLSID
2005
IEEE
16 years 7 months ago
2005
IEEE
A novel topology for Translinear (TL) loops comprising of CMOS Second Generation Current Conveyors (CC-II) and diodes is proposed. The proposed methodology opens a new paradigm to...
163
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ISCAS
2008
IEEE
16 years 1 months ago
2008
IEEE
—A new delta-sigma Analog-to-Digital Converter (ADC) is presented in this paper. A two-step pipeline ADC is used as the quantizer of this delta-sigma modulator to reduce the quan...
170
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ICC
2007
IEEE
16 years 1 months ago
2007
IEEE
—A new network architecture for high-speed low-latency interconnects is introduced, based on a combination of optical wavelength division multiplexing and the automatic packet se...