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DATE
2003
IEEE
130views Hardware» more  DATE 2003»
16 years 1 days ago
Noise Macromodel for Radio Frequency Integrated Circuits
† Noise performance is a critical analog and RF circuit design constraint, and can impact the selection of the IC system-level architecture. It is therefore imperative that some ...
Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi
VL
2003
IEEE
121views Visual Languages» more  VL 2003»
16 years 13 hour ago
Visual methods for web application design
The paper outlines a tool-supported approach to the design of Web applications. Behavioural models are augmented with web-based simulations of user interfaces to permit validation...
Robert Chatley, Jeff Kramer, Jeff Magee, Sebasti&a...
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
15 years 11 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ISCA
1998
IEEE
129views Hardware» more  ISCA 1998»
15 years 11 months ago
Memory System Characterization of Commercial Workloads
Commercial applications such as databases and Web servers constitute the largest and fastest-growing segment of the market for multiprocessor servers. Ongoing innovations in disk ...
Luiz André Barroso, Kourosh Gharachorloo, E...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
15 years 11 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick