3395 search results - page 298 / 679 » Circuit-aware architectural simulation |
159
Voted
DAC
1996
ACM
15 years 10 months ago
1996
ACM
: While delay modeling of gates with a single switching input has received considerable attention, the case of multiple inputs switching in close temporal proximity is just beginni...
157
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ISLPED
1996
ACM
15 years 10 months ago
1996
ACM
This paper examines the energy delay implications of partial product reduction methods employed in parallel multiplier implementations. Radix 4 Modified Booth Algorithm (MBA) is c...
172
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ISCA
1994
IEEE
15 years 10 months ago
1994
IEEE
This paper evaluates the tradeoffs involved in the design of the software-extended memory system of Alewife, a multiprocessor architecturethat implements coherentsharedmemorythrou...
194
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ISCAS
1994
IEEE
15 years 10 months ago
1994
IEEE
This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units...
174
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ASPLOS
1994
ACM
15 years 10 months ago
1994
ACM
There is an increasing trend to use commodity microprocessors as the compute engines in large-scale multiprocessors. However, given that the majority of the microprocessors are so...