Sciweavers

3395 search results - page 288 / 679
» Circuit-aware architectural simulation
Sort
View
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
16 years 1 months ago
UMTS MPSoC design evaluation using a system level design framework
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
Douglas Densmore, Alena Simalatsar, Abhijit Davare...
ESTIMEDIA
2004
Springer
16 years 1 days ago
A queuing-theoretic performance model for context-flow system-on-chip platforms
Abstract—Few analytical performance models that relate performance figure of merit to architectural design decisions are reported in recent studies of network-on-chip, which pre...
Rami Beidas, Jianwen Zhu
IPPS
2000
IEEE
15 years 11 months ago
Performance of On-Chip Multiprocessors for Vision Tasks
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Vi...
JUCS
2006
112views more  JUCS 2006»
15 years 6 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi
JOIN
2007
96views more  JOIN 2007»
15 years 6 months ago
Universal Routing and Performance Assurance for Distributed Networks
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
Kevin F. Chen, Edwin Hsing-Mean Sha