3395 search results - page 287 / 679 » Circuit-aware architectural simulation |
199
click to vote
CGO
2003
IEEE
15 years 12 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
243
click to vote
COOPIS
2002
IEEE
15 years 11 months ago
2002
IEEE
Rapid advances in networking, hardware, and middleware technologies are facilitating the development and deployment of complex grid applications, such as large-scale distributed co...
187
click to vote
ISCA
2000
IEEE
15 years 11 months ago
2000
IEEE
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
191
click to vote
DATE
2008
IEEE
16 years 1 months ago
2008
IEEE
Accurate power and performance figures are critical to assess the effective design of possible sensor node architectures in Body Area Networks (BANs) since they operate on limite...
174
click to vote
3DIC
2009
IEEE
16 years 1 months ago
2009
IEEE
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...