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ICPP
2008
IEEE
16 years 1 months ago
Optimizing Issue Queue Reliability to Soft Errors on Simultaneous Multithreaded Architectures
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
Xin Fu, Wangyuan Zhang, Tao Li, José A. B. ...
INFOCOM
2007
IEEE
16 years 29 days ago
A Cross-Layer Architecture to Exploit Multi-Channel Diversity with a Single Transceiver
—The design of multi-channel multi-hop wireless mesh networks is centered around the way nodes synchronize when they need to communicate. However, existing designs are confined ...
Jay A. Patel, Haiyun Luo, Indranil Gupta
FCCM
2006
IEEE
113views VLSI» more  FCCM 2006»
16 years 21 days ago
GraphStep: A System Architecture for Sparse-Graph Algorithms
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
Michael DeLorimier, Nachiket Kapre, Nikil Mehta, D...
ICNP
2006
IEEE
16 years 21 days ago
RAIN: A Reliable Wireless Network Architecture
Abstract— Despite years of research and development, pioneering deployments of multihop wireless networks have not proven successful. The performance of routing and transport is ...
Chaegwon Lim, Haiyun Luo, Chong-Ho Choi
187
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IISWC
2006
IEEE
16 years 21 days ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...