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CODES
2005
IEEE
16 years 8 days ago
Power-smart system-on-chip architecture for embedded cryptosystems
In embedded cryptosystems, sensitive information can leak via timing, power, and electromagnetic channels. We introduce a novel power-smart system-on-chip architecture that provid...
Radu Muresan, Haleh Vahedi, Y. Zhanrong, Stefano G...
IEEEPACT
2005
IEEE
16 years 7 days ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
INFOCOM
2003
IEEE
15 years 12 months ago
S-MIP: A Seamless Handoff Architecture for Mobile IP
—As the number of Mobile IP (MIP) [2] users grow, so will the demand for delay sensitive real-time applications, such as audio streaming, that require seamless handoff, namely, a...
Robert Hsieh, Zhe Guang Zhou, Aruna Seneviratne
DAC
2006
ACM
16 years 7 months ago
A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
HPCA
2005
IEEE
16 years 7 months ago
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihi...