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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 28 days ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
NOSSDAV
2005
Springer
16 years 4 days ago
MOPAR: a mobile peer-to-peer overlay architecture for interest management of massively multiplayer online games
In this paper we propose a fully distributed peer-to-peer (P2P) infrastructure supporting Networked Virtual Environment (NVE) applications, such as massively multiplayer online ga...
Anthony (Peiqun) Yu, Son T. Vuong
GECCO
2004
Springer
145views Optimization» more  GECCO 2004»
16 years 1 days ago
Search Based Automatic Test-Data Generation at an Architectural Level
Abstract. The need for effective testing techniques for architectural level descriptions is widely recognised. However, due to the variety of domain-specific architectural descript...
Yuan Zhan, John A. Clark
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 7 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
ICCAD
2003
IEEE
136views Hardware» more  ICCAD 2003»
16 years 3 months ago
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications
— Memory-intensive applications present unique challenges to an ASIC designer in terms of the choice of memory organization, memory size requirements, bandwidth and access latenc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...