Sciweavers

3395 search results - page 275 / 679
» Circuit-aware architectural simulation
Sort
View
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
16 years 8 days ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
HPCA
2008
IEEE
16 years 7 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
IROS
2009
IEEE
170views Robotics» more  IROS 2009»
16 years 1 months ago
A programming architecture for smart autonomous underwater vehicles
— Autonomous underwater vehicles (AUVs) are an indispensable tool for marine scientists to study the world’s oceans. The Slocum glider is a buoyancy driven AUV designed for mis...
Hans C. Woithe, Ulrich Kremer
ASPLOS
2010
ACM
16 years 1 months ago
Cortical architectures on a GPGPU
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
Andrew Nere, Mikko Lipasti
MICRO
2008
IEEE
124views Hardware» more  MICRO 2008»
16 years 1 months ago
SHARK: Architectural support for autonomic protection against stealth by rootkit exploits
Rootkits have become a growing concern in cyber-security. Typically, they exploit kernel vulnerabilities to gain root privileges of a system and conceal malware’s activities fro...
Vikas R. Vasisht, Hsien-Hsin S. Lee