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ISLPED
2003
ACM
155views Hardware» more  ISLPED 2003»
15 years 12 months ago
Low-power high-level synthesis for FPGA architectures
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
Deming Chen, Jason Cong, Yiping Fan
GLVLSI
2010
IEEE
136views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Thermal-aware compilation for system-on-chip processing architectures
The development of compiler-based mechanisms to reduce the percentage of hotspots and optimize the thermal profile of large register files has become an important issue. Thermal...
Mohamed M. Sabry, José L. Ayala, David Atie...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
15 years 11 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
MSWIM
2006
ACM
16 years 18 days ago
The effect of the radio wave propagation model in mobile ad hoc networks
The simulation of wireless networks has been an important tool for researchers and the industry in the last years. Especially in the field of Mobile Ad Hoc Networking, most curre...
Arne Schmitz, Martin Wenig
MSWIM
2005
ACM
16 years 6 days ago
Huginn: a 3D visualizer for wireless ns-2 traces
Discrete-event network simulation is a major tool for the research and development of mobile ad-hoc networks (MANETs). These simulations are used for debugging, teaching, understa...
Björn Scheuermann, Holger Füßler, ...