3395 search results - page 260 / 679 » Circuit-aware architectural simulation |
159
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SIGSOFT
2000
ACM
15 years 11 months ago
2000
ACM
Designing architectural frameworks without the aid of formal modeling is error prone. But, unless supported by analysis, formal modeling is prone to its own class of errors, in wh...
211
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VLSID
2004
IEEE
16 years 7 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
209
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HPCA
2001
IEEE
16 years 7 months ago
2001
IEEE
This paper introduces a router delay model that accurately models key aspects of modern routers. The model accounts for the pipelined nature of contemporary routers, the specific ...
167
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GLOBECOM
2008
IEEE
16 years 1 months ago
2008
IEEE
— Time-interleaved (TI) analog-to-digital converters (ADCs) are a promising architecture for realizing the highspeed ADCs required to implement “mostly digital” receivers for...
174
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INFOCOM
2008
IEEE
16 years 1 months ago
2008
IEEE
—All-Optical Label Swapping (AOLS) forms a key technology towards the implementation of All-Optical Packet Switching nodes (AOPS) for the future optical Internet. The capital exp...