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ICIP
2003
IEEE
16 years 8 months ago
Embedded co-processor architecture for CMOS based image acquisition
This paper describes a new co-processor architecture designed for CMOS sensor imaging. The co-processor unit is integrated into the image acquisition loop so as to exploit the ful...
Julien Dubois, Marco Mattavelli
ICIP
1999
IEEE
16 years 8 months ago
An End-To-End Architecture for Mpeg-4 Video Streaming over the Internet
It is a challenging problem to design an e cient MPEG-4 video delivery system that can maximize the perceptual quality while achieving high resource utilization. This paper addres...
Yiwei Thomas Hou, Dapeng Wu, Wenwu Zhu, Hung-Ju Le...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
16 years 1 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
ICC
2008
IEEE
121views Communications» more  ICC 2008»
16 years 1 months ago
iREX MPO : A Multi-Path Option for the iREX Inter-Domain QoS Policy Architecture
Abstract—The inter-domain Resource Exchange (iREX) architecture uses economic market mechanisms to automate the deployment of end-to-end (E2E) inter-domain (ID) quality of servic...
Ariffin Datuk Yahaya, Tatsuya Suda
ISCC
2008
IEEE
16 years 1 months ago
A Partially Buffered Crossbar packet switching architecture and its scheduling
The crossbar fabric is widely used as the interconnect of high-performance packet switches due to its low cost and scalability. There are two main variants of the crossbar fabric:...
Lotfi Mhamdi