3395 search results - page 239 / 679 » Circuit-aware architectural simulation |
174
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FPGA
2003
ACM
15 years 11 months ago
2003
ACM
This paper presents a flexible FPGA architecture evaluation framework, named fpgaEVA-LP, for power efficiency analysis of LUT-based FPGA architectures. Our work has several contri...
181
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ICCAD
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
197
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ISQED
2007
IEEE
16 years 26 days ago
2007
IEEE
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
182
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ISCA
2008
IEEE
16 years 1 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
161
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MICRO
2008
IEEE
16 years 1 months ago
2008
IEEE
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...