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DAC
2011
ACM
14 years 6 months ago
Synchronous sequential computation with molecular reactions
Just as electronic systems implement computation in terms of voltage (energy per unit charge), molecular systems compute in terms of chemical concentrations (molecules per unit vo...
Hua Jiang, Marc D. Riedel, Keshab K. Parhi
DAC
2012
ACM
13 years 9 months ago
Chisel: constructing hardware in a Scala embedded language
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
16 years 7 months ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
HPCA
2001
IEEE
16 years 7 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
ICCD
2004
IEEE
129views Hardware» more  ICCD 2004»
16 years 3 months ago
Cache Array Architecture Optimization at Deep Submicron Technologies
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
Annie (Yujuan) Zeng, Kenneth Rose, Ronald J. Gutma...