3395 search results - page 223 / 679 » Circuit-aware architectural simulation |
169
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
162
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DAC
2010
ACM
15 years 10 months ago
2010
ACM
State-of-the-art automatic reliability analyses as used in system-level design approaches mainly rely on Binary Decision Diagrams (BDDs) and, thus, face two serious problems: (1) ...
153
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ANSS
2001
IEEE
15 years 10 months ago
2001
IEEE
In this work, we study the different buffering techniques used in the literature to solve the contention problem in A TM switching architectures. The objective of our study is to ...
183
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GLOBECOM
2009
IEEE
15 years 9 months ago
2009
IEEE
—Wireless mesh networks (WMNs) have recently emerged to be a cost-effective solution to support large-scale wireless Internet access. One important component of realizing large-s...
165
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper describes a novel technique called Embedded Test-bench Control (ETC), extensively used in the verification of Tensilica’s latest configurable processor. Conventional ...