Sciweavers

3395 search results - page 219 / 679
» Circuit-aware architectural simulation
Sort
View
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
15 years 11 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez
PAM
2004
Springer
15 years 12 months ago
Measurements and Laboratory Simulations of the Upper DNS Hierarchy
Given that the global DNS system, especially at the higher root and top-levels, experiences significant query loads, we seek to answer the following questions: (1) How does the ch...
Duane Wessels, Marina Fomenkov, Nevil Brownlee, Ki...
AINA
2009
IEEE
16 years 1 months ago
Predictive Simulation of HPC Applications
The architectures which support modern supercomputing machinery are as diverse today, as at any point during the last twenty years. The variety of processor core arrangements, thr...
Simon D. Hammond, J. A. Smith, Gihan R. Mudalige, ...
DAC
2002
ACM
16 years 7 months ago
A framework for evaluating design tradeoffs in packet processing architectures
We present an analytical method to evaluate embedded network packet processor architectures, and to explore their design space. Our approach is in contrast to those based on simul...
Lothar Thiele, Matthias Gries, Samarjit Chakrabort...
SAMOS
2009
Springer
16 years 1 months ago
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
We believe that future many-core architectures should support a simple and scalable way to execute many threads that are generated by parallel programs. A good candidate to impleme...
Roberto Giorgi, Zdravko Popovic, Nikola Puzovic