3395 search results - page 198 / 679 » Circuit-aware architectural simulation |
103
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ITC
2003
IEEE
15 years 11 months ago
2003
IEEE
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
154
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ISCA
2008
IEEE
16 years 28 days ago
2008
IEEE
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
152
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MICRO
2007
IEEE
16 years 24 days ago
2007
IEEE
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use of statistical simulation, evaluation of a sing...
226
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
190
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...