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IPPS
2007
IEEE
16 years 23 days ago
Rethinking Automated Synthesis of MPSoC Architectures
Emerging heterogeneous multiprocessors will have custom memory and bus architectures that must balance resource sharing and system partitioning to meet cost constraints. We propos...
Brett H. Meyer, Donald E. Thomas
AHS
2006
IEEE
152views Hardware» more  AHS 2006»
16 years 16 days ago
Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC
This paper describes the architecture of our dynamically reconfigurable Network-on-Chip (NoC) architecture that has been proposed for reconfigurable Multiprocessor system-on-chip ...
Balal Ahmad, Ahmet T. Erdogan, Sami Khawam
ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
16 years 2 days ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
ICRA
2002
IEEE
124views Robotics» more  ICRA 2002»
15 years 11 months ago
Open Architecture Humanoid Robotics Platform
This paper introduces an open architecture humanoid robotics platform (OpenHRP for short) on which various building blocks of humanoid robotics can be investigated. OpenHRP is a v...
Fumio Kanehiro, Kiyoshi Fujiwara, Shuuji Kajita, K...
ISLPED
1999
ACM
84views Hardware» more  ISLPED 1999»
15 years 10 months ago
An architectural solution for the inductive noise problem due to clock-gating
As we approach Gigascale Integration, chip power consumption is becoming a critical system parameter. Clock-gating idle units provides needed reductions in power consumption. Howe...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...