3395 search results - page 168 / 679 » Circuit-aware architectural simulation |
177
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ICMCS
2006
IEEE
16 years 15 days ago
2006
IEEE
In this work, we develop a hierarchical load testing architecture using large scale virtual clients to reduce the testing time and ensure the stability of the server for distribut...
164
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3DIC
2009
IEEE
15 years 11 months ago
2009
IEEE
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
126
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ISSS
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
169
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VLSID
2000
IEEE
15 years 11 months ago
2000
IEEE
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
164
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DATE
2006
IEEE
16 years 16 days ago
2006
IEEE
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...